Low Power Hardware Trojan Detection, Identification, and Recovery Mechanism
- Kisaru Liyanage
- Chathura Nagoda Gamage
- Prof. Roshan G. Ragel
- Dr. Isuru Nawinne
The security and reliability of an Integrated Circuit (IC) are challenged by the possibility of hardware Trojans being inserted into it during its development process. A malicious third party who involves in any phase of IC development process could inject a hardware Trojan to make the circuit deviate from its intended function or leak sensitive data processed by the circuit. Many prevention mechanisms and countermeasures have been proposed to overcome the hardware Trojans due to the adverse effects of them on crucial systems. In this paper, we discuss the state-of-the-art Triple Modular Redundancy (TMR) based hardware Trojan detection, identification, and recovery mechanism. Then we present a novel mechanism based on Dual Modular Redundancy (DMR) to improve the dynamic power consumption of the TMR mechanism. Moreover, we implement an automation framework to generate the above secure systems in less than 50 milliseconds. Finally, we evaluate the generated secure systems using a standard benchmark, AES.