Power Aware High-Level Synthesis Flow for Mapping Large-Scale FPGA Designs

Present Field Programmable Gate Array (FPGA) manufacturers incorporate multi-millions of logic resources which enables hardware designers to design applications extend ing to enormous scales. However, handling such applications by existing FPGA Computer Aided Design (CAD) flow requires more improvement in terms of compilation time, performance and power efficiency considerations. However, the existing CAD flow requires the input design to be in Register Transfer Level (RTL). This limits the design productivity only to hardware experts in performing analysis for optimizations on large-scale designs. Optimizing larger RTL designs manually is increasingly difficult. High-Level Synthesis (HLS) is an approach capable of increasing the design productivity of hardware applications compared to commonly used Hardware Description Languages (HDLs) and is known to be a capable approach for performing optimizations at a higher level of abstraction. Our concern is to propose an approach that follows the HLS flow to cater the mapping of large scale applications to FPGA in a power efficient manner. From our experiments, it was possible to achieve an average reduction of 6.7% routing thermal power and 2.42% total power.