RV32IM Pipeline Implementation Group1
Created: 02-02-2025 Forks: 0 Watchers: 1 Stars: 1
Description
This repository contains an implementation of a RISC-V RV32IM processor with a 5-stage pipeline architecture. The design includes instruction fetch, decode, execute, memory access, and write-back. It supports integer operations, multiplication, and memory access as defined in the RV32IM instruction set.
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