PeraMorphIQ

Brain-inspired hardware for energy-efficient intelligence at the edge.

PeraMorphIQ is a neuromorphic computing research group at the Department of Computer Engineering, University of Peradeniya, and is part of ESCAL (Embedded Systems and Computer Architecture Laboratory) under PeraCom. The group designs neuromorphic architectures for spiking neural networks, from accelerator microarchitecture and RISC-V System-on-Chip integration through to FPGA prototypes and silicon analysis.

Our work runs end to end, from simulation frameworks and algorithmic exploration through FPGA prototypes to ASIC implementation. We build configurable neuromorphic accelerators with on-chip learning, memory and power optimisation, and real-time processing suited to embedded deployment. By bridging neuroscience, machine learning and embedded systems, we aim at computing platforms that borrow the adaptability and energy efficiency of biological neural systems, and are small enough to actually deploy.

Research areas

Four connected threads, from the neuron model up to a deployable system-on-chip.

• Neuromorphic accelerators — Configurable accelerator microarchitectures for spiking networks, designed for the small-scale regime where embedded and edge workloads actually sit.
• Spiking neural networks & on-chip learning — Hardware-realisable learning rules and the weight-update paths that let a deployed device adapt without a round trip to a host machine.
• RISC-V SoC & Network-on-Chip — Custom ISA extensions, network interfaces and 2D-mesh interconnect that turn a general-purpose open ISA into a spiking-network substrate.
• Edge AI hardware — Memory organisation, power optimisation and FPGA-to-ASIC paths that bring real-time inference within the energy budget of an edge device.

Featured projects

• SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks (E19 Final Year Project, 2024–present) — A RISC-V neuromorphic SoC with two accelerator variants, Cerebra-S (bus-based) and Cerebra-H (NoC-based), optimised for small-scale SNN inference at 1.05 pJ per synaptic operation.
• On-Chip Offline Neuromorphic Computing (E20 Final Year Project, 2025–present) — A custom RISC-V CPU with a six-instruction ISA extension for on-chip spiking neural network backpropagation training, running without any host PC.
• On-Chip Online Learning for Neuromorphic Hardware (E20 Final Year Project, 2025–present) — Learning rules implemented directly in neuromorphic hardware, so a deployed device can adapt online without a round trip to a host machine.
• PeraMorphIQ SRAM Compiler (Open-source tool, 2026–present) — A streamlined, automated workflow for generating custom SRAM macros, built on the OpenRAM framework and released publicly for the open-source hardware community.

Selected publications

• Neuromorphic architectures for edge-oriented spiking neural networks: A review
  Kanishka Gunawardana, Sanka Peeris, Kavishka Rambukwella, Roshan Ragel, Isuru Nawinne
  Journal of Systems Architecture, 177, 103869 (2026) · Open access (CC BY 4.0)
  doi: 10.1016/j.sysarc.2026.103869
• SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
  Kanishka Gunawardana, Sanka Peeris, Kavishka Rambukwella, Thamish Wanduragala, Saadia Jameel, Roshan Ragel, Isuru Nawinne
  arXiv preprint (2026) · Open access
  doi: 10.48550/arXiv.2603.11939
• RV32IMF Five-Stage Pipeline Implementation with Interrupt and Random Number Generation Units
  Dinindu Thilakarathna, Heshan Dissanayake, Roshan Ragel, Isuru Dasanayake, Mahanama Wickramasinghe
  2023 IEEE 17th International Conference on Industrial and Information Systems (ICIIS) (2023)
  doi: 10.1109/ICIIS58898.2023.10253607

Work with us

We supervise final-year and graduate projects, and we welcome collaboration with research groups and industry partners working on neuromorphic and edge AI hardware.

For the details, feel free to contact Dr. Isuru Nawinne and/or Prof. Roshan Ragel, or write to peramorphiq@eng.pdn.ac.lk.